Tape automated bonded (TAB) circuit

ABSTRACT

A tape automated bonded circuit comprising a flexible substrate having an opening defined by a peripheral sidewall. A plurality of conductive traces are provided on the flexible substrate which terminate in a plurality of leads which extend into alignment with the opening. An electronic device having a plurality of pad regions is aligned with the opening in the substrate. The leads are bonded to the pad regions. A continuous encapsulation layer which touches the peripheral side wall of the substrate opening on all sides encapsulatingly covers the bonded leads and pad regions and structurally reinforces each lead along the entire length which projects over the opening.

BACKGROUND OF THE INVENTION

The present invention generally relates to tape automated bonded (TAB)circuits, and more particularly to a TAB circuit which comprise anencapsulation layer applied over lead/pad bonding regions of thecircuit.

The rapid development of new and advanced microelectronic devices hascreated a corresponding need for improved circuit mounting structures.One type of circuit mounting structure currently in use is called a tapeautomated bonded circuit, commonly known as a "TAB" circuit.

TAB circuits were first researched and developed in the mid-1960's. Asdiscussed in Rima, P. W., "The Basics of Tape Automated Bonding," HybridCircuit Technology, November 1984, pp. 15-21, a TAB circuit isconstructed using a thin film carrier tape which is typically stored onlarge reels. The tape has a variable width of between 8 and 70 mm, andis approximately 5 mils thick. The length of each portion of tape usedto form an individual circuit package is selectively variable, dependingon the type of circuit to be made. The tape may be manufactured from avariety of different dielectric materials, including polyimide, and/orepoxy-glass compositions. Polyimide is generally preferred in that ithas a high degree of mechanical strength, is capable of withstandingrelatively high temperatures, and has a high coefficient of linearexpansion similar to that of copper. It also has a relatively lowcoefficient of moisture absorption (about 3%).

There are numerous methods which may be used to construct TAB circuits.See, for example, U.S. Pat. No. 4,944,850 of John H. Dion et al., whichis hereby specifically incorporated by reference for all that itdiscloses. One method (known as the "three layer process") involves theuse of a thin, conductive foil typically manufactured of copper orcopper alloy which is bonded to the tape using an adhesive known in theart. The foil is approximately 1.4 mils thick in a typical embodiment.In addition, an opening or window is physically formed through thecenter of each portion or "frame" of tape by chemical etching or otherconventional means, including the use of a punch and die assembly. Thefoil is then etched to produce a conductive printed circuit patternhaving beam-type inner leads which extend into the window.

In an alternative construction method commonly known as the "two layerprocess", a base layer of metal (e.g., copper) is directly sputtered orotherwise deposited onto the tape. Next, the tape substrate is runthrough an electroless bath of metal (e.g., copper) which deposits avery thin layer of metal onto the substrate surface and first metallayer. After window formation as described above, the top layer of metalis covered with a thin layer of photoresist which is imaged anddeveloped, leaving a exposed metal pattern. The patterned substrate ispassed through an electrolytic bath where a further metal layer isplated onto the exposed metal pattern. Resist materials are applied andsubsequently etched to produce the completed product, as discussed inDixon, T., "TAB Technology Tackles High Density Interconnections",Electronic Packaging and Production, pp. 34-39 (December, 1984).

As noted above, the metal used to create the circuit patterns normallyinvolves copper or a copper alloy. These materials have a tendency tocorrode which may adversely affect the operational capabilities of thecircuit. To prevent surface corrosion, the circuit pattern is normallyplated with a non-corrosive metal (e.g., gold, palladium, and/orrhodium.) Typically, the non-corrosive metal is electroplated onto thecircuit pattern. Electroplating is a conventional process, which isnormally accomplished by immersion of the circuit into a bath of metalsolution, followed by the application of a current to the circuit.Simultaneously with the application of current to the circuit, a currentof opposite charge is applied to the metal solution. As a result, metalfrom the solution is plated onto the circuit. So that electrical currentmay be applied to the circuit as described above, all of the circuittraces must be shorted together to ensure complete plating.

After plating, a selected electronic device, e.g. an integrated circuitchip (IC), is positioned within the window and secured therein bybonding the inner leads of the circuit to contact regions on the device.

Historically prior to inner lead bonding, the IC contact or "pad"regions, which are typically aluminum, would have gold bumps platedthereto. The bumping process involves multiple operations in addition tothe standard wafer manufacturing process, increasing the risk of damageto the IC. The bumping process is also a relatively expensive process.In a more recently developed TAB manufacturing process, the gold platedTAB leads are bounded directly to the aluminum bonding pads of the IC,eliminating the need for pad bumping. One manner for achieving suchdirect lead/pad bonding is through one of a single point thermosonicbonding process which may be performed, for example, with a Hughes Model2460-2 Thermosonic Single Point. Bender which is commercially availablefrom Hughes Aircraft having a business address of 2051 Palomar AirportRoad, Carlsbad, Calif., 92009.

When the pad bumping process is employed for achieving lead/pad bonding,the pad region of the IC is completely covered by the bump, protectingit from environmental degradation. The direct lead/pad bonding techniqueis generally preferable to bump bonding from a production coststandpoint. However, a problem with the direct lead/pad bondingtechnique is that it leaves the aluminum pad regions of the connected ICexposed. This shortcoming has been overcome by coating the side of theIC containing the pad regions with a dielectric encapsulation materialwhich seals the aluminum bonding pads from environmental hazards.

Encapsulation material is generally chosen to match the coefficient ofthermal expansion of the IC. An ideal encapsulation material providesprotection from moisture and corrosive environments that the circuit mayencounter. It also is low in alpha particle emissions, acts as asuitable alpha particle barrier, and has flow properties conducive toautomated dispensing. Common encapsulating materials include siliconegels, thermoset epoxies, and polyimide-based coatings.

The encapsulating material is typically dispensed from a dispensingneedle. The needle is positioned above the IC and is moved in anoutwardly spiralling motion as the encapsulating material is dispensed.The encapsulating material is typically applied so as to cover the padside of the IC. The encapsulation layer terminates near the edge of thepad side of the IC in spaced apart relationship with the periphery ofthe opening in the flexible substrate.

This encapsulation technique thus leaves the portion of each of theleads which is positioned over the opening in the flexible substrateexposed to the environment. However, since the leads, like the remainderof the traces, are coated with gold, this would not appear to be aproblem.

SUMMARY OF THE INVENTION

It is applicant's discovery that the inner leads of TAB circuits aresubject to mechanical failure which may result in performancedegradation of the TAB circuit. Applicant has also discovered that theprobability of lead failure in TAB circuits may be reduced by providingthe TAB circuit with an encapsulation layer which extends across the padcontaining surface of the connected IC and into touching relationshipwith the sidewall of the opening in the flexible substrate. Theencapsulation layer when thus applied completely covers and reinforcesthe leads in the portions thereof which extend into alignment with (i.e.which extend over/under) the substrate opening.

Thus, the invention may comprise a method of manufacturing a tapeautomated bonded circuit including the steps of: (a) providing aflexible substrate having an opening therethrough defined by aperipheral sidewall and having a plurality of conductive traces providedthereon which terminate in a plurality of leads which extend intoalignment with the opening; (b) providing an electronic device having aplurality of pad regions thereon; (c) positioning the electronic devicein alignment with the opening in the substrate; (d) bondingly connectingthe leads to the pad regions; and (e) covering the bondingly connectedleads and pad regions with a continuous layer of encapsulation materialwhich touches the peripheral sidewall of the substrate opening.

The invention may also comprise a tape automated bonded circuitcomprising a flexible substrate having an opening therethrough definedby a peripheral sidewall. A plurality of conductive traces are providedon the flexible substrate which terminate in a plurality of leads whichextend into alignment with the opening. An electronic device having aplurality of pad regions thereon is aligned with the opening in thesubstrate. The leads on the substrate are bonded to the pad regions onthe electronic device. A continuous encapsulation layer which touchesthe peripheral side wall of the substrate opening on all sidesencapsulatingly covers the bonded leads and pad regions and structurallyreinforces each lead along the entire length thereof which projects overthe opening.

BRIEF DESCRIPTION OF THE DRAWINGS

An illustrative and presently preferred embodiment of the invention isshown in the accompanying drawings in which:

FIG. 1 is a bottom plan view of a portion of a tape automated bonded(TAB) circuit prior to connection with an IC device.

FIG. 2 is a top plan view of a portion of a TAB circuit subsequent toconnection with an IC device.

FIG. 3 is a detail cross-sectional elevation view of a portion of a TABcircuit prior to application of encapsulation material thereto.

FIG. 4 is a detail cross-sectional elevation view of a portion of a TABcircuit subsequent to application of encapsulation material thereto..

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

With reference to FIGS. 1 and 2, a TAB circuit 10 is illustrated. Thecircuit 10 includes a tape substrate 12 having a first flat face surface11, FIG. 1, and a second flat face surface 13, FIG. 2. The substrate 12is preferably manufactured of polyester, polyimide, or epoxy-glasscompositions. The tape substrate 12 includes a window 14 therethrough ofselectively variable size which is defined by a rectangular sidewall 15.The window 14 is sized to be slightly larger than an integrated circuit(IC) or other electronic device 40 which is positioned in alignment withthe window as shown in phantom.

The tape substrate 12 also includes at least one conductive metal layerin the form of a trace pattern 16 which interfaces with the first facesurface 11 thereof. The trace pattern 16 is typically formed through theattachment of a thin conductive metal foil to the substrate 12 (e.g.,1.4 mil thick copper) using an adhesive known in the art. The foil isthen etched using conventional techniques to produce the trace pattern16. Formation of the trace pattern is described in greater detail inRima, P. W., "The Basic of Tape Automated Bonding," Hybrid CircuitTechnology, November, 1984, pp 15-21. However, there are alternativeways to produce the trace pattern 16 as noted above.

With continued reference to FIGS. 1 and 2, the trace pattern 16 includesa selectively variable quantity of conductive pads 20, each pad 20 beingconductively connected to a lead 22. The pads 20 communicate with leads22 through individual traces which comprise the trace pattern 16. Asshown in FIG. 1, the leads 22 extend outwardly into alignment with thewindow 14, i.e. extends into a three-dimensional region formed byprojecting the window opening 14 normal to surface 11. As discussedherein, this positioning of the lead may alternatively be referred to asprojecting or extending "over" the window. In a preferred embodiment,each lead 22 is approximately 0.002 inch wide and extends out over thewindow 14 by about 0.038 inch, although these values may be varied asdesired. The leads 22 are adapted for subsequent attachment to an IC orother comparable electronic device 40.

Since the leads 22 and trace pattern 16 are normally manufactured ofcopper (or other metal subject to corrosion), a protective coating ofsubstantially inert metal (e.g., gold) is traditionally applied thereto.This is formally accomplished by electroplating processes known in theart which basically involve immersing the trace pattern 16 in a selectedmetal solution, applying a current to the pattern, and applying acurrent of opposite charge to the solution. This results in the platingof metal from the solution onto the trace pattern 16. As indicatedabove, electroplating is a conventional process. The actual electricalcurrents used and metal solutions involved may be selectively varied inaccordance with numerous factors, including the size of the circuit, thematerials used to form the circuit, the desired application for whichthe circuit is intended, etc. Basic techniques for electroplating whichare applicable to the present invention are described in MetalFinishing, Michael Murphy--editor, Metals and Plastics Publications,Hackensack, N.J., Vol. 83, No. 1A (January, 1985); and Lowenheim, F. A.,Electroplating: Fundamentals of Surface Finishing, McGraw-Hill, Inc.,1978.

To accomplish electroplating of the trace pattern 16, all of theindividual traces must be shorted together so that current may flowtherethrough.

Techniques for shorting the traces for electroplating are described inabove-referenced U.S. Pat. No. 4,944,850.

After electroplating, the traces are tested for shorts and opens. Suchtesting techniques are also described in U.S. Pat. No. 4,944,850.

As shown by FIGS. 2-4, electronic device 40 may comprise a flat,rectangularly shaped member having a first generally flat face surface42 and an opposite flat face surface 44 connected by a sidewall 46. Aplurality of exposed contact pads 50 are provided about the periphery ofthe first face surface 42.

The electronic device 40 is positioned in alignment with window 14immediately below substrate surface 11 such that each pad 50 on device40 is positioned in registration with a corresponding lead 22 of tracepattern 16.

The trace leads 22 are fixedly conductively bonded to the pads 50 as bysingle point thermosonic bond 52 such as described in U.S. Pat. No.4,842,662 of John W. Jacobi, which is hereby specifically incorporatedby reference for all that is disclosed therein, or by using otherbonding techniques.

After lead/pad bonding, a layer of encapsulation material 60 is appliedto the first face surface 42 of the electronic device 40 as by anextrusion needle 60. The needle is typically moved in a spirallingmotion above surface 40 as encapsulation material is dispensed therefromat a controlled rate. One assembly for applying encapsulation materialin this manner is sold under the product designation Asymtek Model 403and is commercially available from Asymtek having a business address of1949 Palomar Oaks Way, Carlsbad, Calif., 92009-1307. The encapsulationmaterial used may be any of a number of different materials, includingsilicones, polyimides, and filled epoxies, and is preferably a syntheticsilica filled epoxy such as that manufactured by Hokuriku Toryo Company,Ltd. of Japan, under the product designation Hokuriku Chipcoat 8101,which is commercially available from Pacific Polytech, Inc., 15Commercial Blvd., Novato, Calif., 94949.

The chip 40 or dispense needle 62 may be heated during the dispenseoperation to obtain the desired rheology to obtain uniform coatings thatcompletely cover the surface 42 and interconnections. However, it isgenerally desirable to avoid heating unless absolutely necessary.

Following dispense of encapsulation material, the coating must completea cure process which could be initiated by means of UV radiation,microwave energy, or most preferably, elevated temperature. The elevatedtemperature can be applied by means of conduction heating, IR radiantheating, or convective heating, the preferable method being convectiveheating in an oven environment.

The temperature profile used to cure the encapsulant will be dependenton the encapsulation material. If solvents are present in the dispensedcoating, a slow temperature ramp must be used to prevent the formationof voids that can adversely impact device reliability. When usingsolventless systems, a fast temperature ramp is often performedimmediately following the dispense process to solidify, or "gel", theencapsulation material, making the device less susceptible to handlingdamage during the cure process. This is particularly useful inreel-to-reel TAB processes.

The maximum cure temperature must be sufficient to fully cross-link thepolymer coating. Typical cure cycles involve exposure to temperaturesranging from 130°-200° C. for 30 minutes to 2 hours to obtain full cure.

In applying a synthetic silica filled phenol epoxy, the applicationneedle 62 and IC 40 are maintained at room temperature during theapplication process. Curing may take place in a convection oven using aramped cure. The tab circuit 10 including encapsulation material 60 isinitially heated in the oven at 80° C. for approximately one hour. Then,the oven is ramped up to 150° C. over a period of one-half hour and isthereafter held at 150° C. for approximately one hour to complete theheat cure.

According to the present invention, the encapsulation material isapplied in a manner and in sufficient quantity such that it completelycovers the first face surface 42 of the device 40 and such that itextends into interfacing relationship with the entire peripheralsidewall 15 defining substrate opening 14 and a substantial portion,e.g. 50%, of the sidewall 46 of IC 40 and is itself supported at itsinterface with substrate opening sidewall 15 and IC sidewall 46. Theencapsulation material 60 thus completely covers all portions of theleads 22 which extend out over window 14. In one preferred embodiment,the encapsulation material is applied in a manner such that after curingit is provided with an exposed flat surface portion 64 which isapproximately coplanar with second face surface 13 of flexible substrate12. The encapsulation layer thus applied serves to structurallyreinforce the leads 22 along the entire length of their otherwiseunsupported extension over opening 14.

Applicants have discovered that the structural support to the leads 22which is provided by encapsulation material 60 reduces the probabilityof lead failure and consequent degradation of circuit performance.

While an illustrative and presently preferred embodiment of theinvention has been described in detail herein, it is to be understoodthat the inventive concepts may be otherwise variously embodied andemployed and that the appended claims are intended to be construed toinclude such variations except insofar as limited by the prior art.

What is claimed is:
 1. A tape automated bonded circuit comprising:aflexible substrate having an opening therethrough defined by aperipheral sidewall; a plurality of conductive traces provided on saidflexible substrate which terminate in a plurality of leads which extendinto alignment with said opening; an electronic device having aplurality of pad regions thereon aligned with said opening in saidsubstrate; bonding means for connecting said leads to said pad regions;continuous encapsulation means touching said peripheral side wall ofsaid substrate opening for encapsulatingly covering said bondinglyconnected leads and pad regions and for structurally reinforcing saidleads from said peripheral sidewall of said opening to said bondingmeans; wherein said electronic device comprises a first face, a secondface and a peripheral sidewall extending between said first face andsaid second face, said plurality of pad regions being provided on saidfirst face; wherein said continuous encapsulation means covers theentire first face of said electronic device and at least a portion ofsaid peripheral sidewall of said electronic device and wherein saidsecond face of said electronic device is exposed; wherein said substratecomprises a first flat face which interfaces with said traces and asecond flat face positioned opposite to said first face thereof; andwherein said electronic device is positioned outside of said opening insaid substrate with said first face of said substrate positionedproximal said first face of said electronic device and said second faceof said substrate positioned distal said first face of said electronicdevice.
 2. The invention of claim 1 wherein said opening in saidsubstrate is entirely filled by said continuous encapsulation means andwherein said continuous encapsulation means comprises a flat surfaceextending in substantially coplanar relationship with said second flatface of said substrate.
 3. The invention of claim 2 wherein saidencapsulation means comprises filled epoxy.
 4. The invention of claim 2wherein said encapsulation means is positioned entirely between a firstplane defined by said second flat surface of said substrate and a secondplane defined by said second face of said electronic device.